Characterization of the Electromagnetic Susceptibility of Integrated Circuits using a Near Field Scan

2 pagesInternational audienceThe paper describes a susceptibility characterization test for integrated circuits using a miniature magnetic near field probe. The method is efficient up to a frequency of 6 GHz and maps immunity to radiated fields

Etude de l'immunité des circuits intégrés face aux agressions électromagnétiques (proposition d'une méthode de prédiction des couplages des perturbations en mode conduit)

Avec les progrès technologiques réalisés au cours de ces dernières décennies, la complexité et les vitesses de fonctionnement des circuits intégrés ont beaucoup été augmentées. Bien que ces évolutions aient permis de diminuer les dimensions et les tensions d alimentations des circuits, la compatibilité électromagnétique (CEM) des composants a fortement été dégradée. Identifiée comme étant un verrou technologique, la CEM est aujourd hui l une des principales causes de re-design des circuits car les problématiques liées aux mécanismes de génération et de couplage du bruit ne sont pas suffisamment étudiées lors de leur conception.Ce manuscrit présente donc une méthodologie visant à étudier la propagation du bruit à travers les circuits intégrés par mesures et par simulations. Afin d améliorer nos connaissances sur la propagation d interférences électromagnétiques (IEM) et les mécanismes de couplage à travers les circuits, nous avons conçu un véhicule de test développé dans la technologie SMOS8MV® 0,25 m de Freescale Semiconductor. Dans ce circuit, plusieurs fonctions élémentaires telles qu un bus d E/S et des blocs numériques ont été implémentées. Des capteurs de tensions asynchrones ont également été intégrés sur différentes alimentations de la puce pour analyser la propagation des perturbations injectées sur les broches du composant (injection DPI) et sur les conducteurs permettant d alimenter ce dernier (injection BCI). En outre, nous proposons différents outils pour faciliter la modélisation et les simulations d immunité des circuits intégrés (extraction des modèles de PCB, approches de modélisation des systèmes d injection, méthode innovante permettant de prédire et de corréler les niveaux de tension/ de puissance injectés lors de mesures d immunité conduite, flot de modélisation). Chaque outil et méthode de modélisation proposés sont évalués sur différents cas test. Enfin, pour évaluer notre démarche de modélisation, nous l appliquons sur un bloc numérique de notre véhicule de test et comparons les résultats de simulations aux différentes mesures internes et externes réalisées sur le circuitWith technological advances in recent decades, the complexity and operating speeds of integrated circuits have greatly increased. While these developments have reduced dimensions and supply voltages of circuits, electromagnetic compatibility (EMC) of components has been highly degraded. Identified as a technological lock, EMC is now one of the main causes of circuits re-designs because issues related to generating and coupling noise mechanisms are not sufficiently studied during their design. This manuscript introduces a methodology to study propagation of electromagnetic disturbances through integrated circuits by measurements and simulations. To improve our knowledge about propagation of electromagnetic interferences (EMI) and coupling mechanisms through integrated circuits, we designed a test vehicle developed in the SMOS8MV® 0.25 m technology from Freescale Semiconductor. In this circuit, several basic functions such as I/O bus and digital blocks have been implemented. Asynchronous on-chip voltage sensors have also been integrated on different supplies of the chip to analyze propagation of disturbances injected on supply pins and wires of the component (DPI and BCI injection). In addition, we propose various tools to facilitate modeling and simulations of Integrated Circuit s immunity (PCB model extraction, injection systems modeling approaches, innovative method to predict and correlate levels of voltage / power injected during conducted immunity measurements, modeling flow). Each tool and modeling method proposed is evaluated on different test cases. To assess our modeling approach, we finally apply it on a digital block of our test vehicle and compare simulation results to various internal and external measurements performed on the circuitTOULOUSE-INSA-Bib. electronique (315559905) / SudocSudocFranceF

An On-Chip Sensor for Time Domain Characterization of Electromagnetic Interferences

International audienceWith the growing concerns about susceptibility of integrated circuits to electromagnetic interferences, the need for accurate prediction tools and models to reduce risks of noncompliance becomes critical for circuit designers. However, on-chip characterization of noise is still necessary for model validation. This paper presents an on-chip noise sensor dedicated to the time-domain measurement of voltage fluctuations induced by interference coupling

On the Susceptibility of Micro-controller to Radio Frequency Interference

International audienceElectromagnetic compatibility (EMC) has recently focused more attention on Integrated Circuits (ICs). This work deals with immunity of micro-controllers to Radio Frequency Interference (RFI). The susceptibility test methods are reviewed, the test bench setup in our labs is presented, and some aspects of defensive software are detailed

Ageing effect on electromagnetic susceptibility of a phase locked loop

5 pagesInternational audiencePhase locked loop in radiofrequency and mixed signal integrated circuit experience noise as electromagnetic interference coupled on input and power supply which translates to the timing jitter. Most of PLL noise analysis did not take into account the ageing effect. However device ageing can degrade the physical parameters of transistors and makes noise impact worse. This paper deals with the analyses of PLL immunity drift after accelerated ageing

Characterisation of electromagnetic compatibility drifts of nanoscale integrated circuit after accelerated life tests

2 pagesInternational audiencePresented is an original study about the effects of integrated circuit aging on electromagnetic emission and immunity to radio frequency interferences. For the first time an electromagnetic compatibility (EMC) qualification procedure is proposed to quantify the EMC level variation over the full lifetime of a component. Results presented show non-negligible variations of the emission and immunity thresholds after accelerated life tests, which could seriously deteriorate EMC margins required to ensure compliance with standard EMC levels

Iterative methods for scattering problems in isotropic or anisotropic elastic waveguides

International audienceWe consider the time-harmonic problem of the diffraction of an incident propagative mode by a localized defect, in an infinite straight isotropic elastic waveguide. We propose several iterative algorithms to compute an approximate solution of the problem, using a classical finite element discretization in a small area around the perturbation, and a modal expansion in unbounded straight parts of the guide. Each algorithm can be related to a so-called domain decomposition method, with or without an overlap between the domains. Specific transmission conditions are used, so that only the sparse finite element matrix has to be inverted, the modal expansion being obtained by a simple projection, using the Fraser bi-orthogonality relation. The benefit of using an overlap between the finite element domain and the modal domain is emphasized, in particular for the extension to the anisotropic case. The transparency of these new boundary conditions is checked for two- and three-dimensional anisotropic waveguides. Finally, in the isotropic case, numerical validation for two- and three-dimensional waveguides illustrates the efficiency of the new approach, compared to other existing methods, in terms of number of iterations and CPU time

Characterization of the Evolution of IC Emissions after Accelerated Aging

9 pagesInternational audienceWith the evolving technological development of integrated circuits (ICs), ensuring electromagnetic compatibility (EMC) is becoming a serious challenge for electronic circuit and system manufacturers. Although electronic components must pass a set of EMC tests to ensure safe operations, the evolution over time of EMC is not characterized and cannot be accurately forecast. This paper presents an original study about the consequences of the aging of circuits on electromagnetic emission. Different types of standard applicative and accelerated-life tests are applied on a mixed power circuit dedicated to automotive applications. Its conducted emission is measured before and after these tests showing variations in EMC performances. Comparisons between each type of aging procedure show that the emission level of the circuit under test is affected differently

On-Chip Noise Sensor for Integrated Circuit Susceptibility Investigations

page number: 12International audienceWith the growing concerns about electromagnetic compatibility of integrated circuits, the need for accurate prediction tools and models to reduce risks of non-compliance becomes critical for circuit designers. However, on-chip characterization of noise is still necessary for model validation and design optimization. Although different on-chip measurement solutions have been proposed for emission issue characterization, no on-chip measurement methods have been proposed to address the susceptibility issues. This paper presents an on-chip noise sensor dedicated to the study of circuit susceptibility to electromagnetic interferences. A demonstration of the sensor measurement performances and benefits is proposed through a study of the susceptibility of a digital core to conducted interferences. Sensor measurements ensure a better characterization of actual coupling of interferences within the circuit and a diagnosis of failure origins

Experimental verification of the usefulness of the nth power law MOSFET model under hot carrier wearout

4 pagesInternational audienceIn this paper the usefulness of the nth power law MOSFET model under Hot Carrier Injection (HCI) wearout has been experimentally demonstrated. In order to do that, three types of nFET transistors have been analyzed under different HCI conditions and the nth power law MOSFET model has been extracted for each sample. The results show that the model can reproduce the MOSFET behavior under HCI wearout mechanism. Therefore, the impact of HCI on circuits can be analyzed by using the nth power law MOSFET model